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Novel Implementation of Recursive Discrete Wavelet Transform for Real Time Computation with Multicore Systems on Chip (SOC)
Mohammad Wadood Majid,
Golrokh Mirzaei,
Mohsin M. Jamali
Issue:
Volume 2, Issue 2, April 2013
Pages:
22-28
Received:
24 February 2013
Accepted:
Published:
2 April 2013
Abstract: The discrete wavelet Transform (DWT) has been studied and developed in various scientific and engineering fields. Its multi-resolution and locality nature facilitates application required for progressiveness in capturing high-frequency details. However, when dealing with enormous data volume, the performance may drastically reduce. The multi-resolution sub-band encoding provided by DWT enables for higher compression ratios, and progressive transformation of signals. The widespread usage of the DWT has motivated the development of fast DWT algorithms and their tuning on all sorts of computer systems. However, this transformation comes at the expense of additional computational complexity. Achieving real-time or interactive compression/de-compression speed, therefore, requires a fast implementation of DWT that leverages emerging parallel hardware systems. The recent advancement in the consumer level multicore hardware is equipped with Single Instruction and Multiple Data (SIMD) power.In this study, Parallel Discrete Wavelet Transform has been developed with novel Adaptive Load Balancing Algorithm (ALBA). The DWT is parallelized, partitioned, mapped and scheduled on single core and Multicore. The Parallel DWT is developed in C# for single and Intel Quad cores as well as the combination of C and CUDA is implemented on GPU. This brings the significant performance on a consumer level PC without extra cost.
Abstract: The discrete wavelet Transform (DWT) has been studied and developed in various scientific and engineering fields. Its multi-resolution and locality nature facilitates application required for progressiveness in capturing high-frequency details. However, when dealing with enormous data volume, the performance may drastically reduce. The multi-resolu...
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Parallel Implementation of the Wideband DOA Algorithm on Single Core, Multicore, Gpu and Ibm Cell be Processor
Mohammad Wadood Majid,
Todd E. Schmuland,
Mohsin M. Jamali
Issue:
Volume 2, Issue 2, April 2013
Pages:
29-36
Received:
3 April 2013
Accepted:
Published:
2 April 2013
Abstract: The Multiple Signal Classification (MUSIC) algorithm is a powerful technique for determining the Direction of Arrival (DOA) of signals impinging on an antenna array.The algorithm is serial based, mathematically intensive, and requires substantial computing power to realize in real-time.Recently, multi-core processors are becoming more prevalent and af-fordable.The challenge of adapting existing serial based algorithms to parallel based algorithms suitable for today’s mul-ti-core processors is daunting. DOA algorithm has been implemented on Multicore (Intel Nehalem Quad Core), NVIDIA’s GPU GeForce GTX 260, and IBM Cell Broadband Engine Processor. This is in an effort to use DOA for real time applications. The DOA algorithm has been parallelized, partitioned, mapped, and scheduled on Multi-Core, GPU, and IBM Cell BE processor.The parallel algorithm is developed in C# for Intel Nehalem Quad Core, a combination of C and CUDA for GPU, and C++ for IBM Cell processor. The algorithm has also been implemented on single core for comparison purposes. Wideband DOA algorithm is implemented assuming 16 and 4 sensors using Uniform Linear Array (ULA).
Abstract: The Multiple Signal Classification (MUSIC) algorithm is a powerful technique for determining the Direction of Arrival (DOA) of signals impinging on an antenna array.The algorithm is serial based, mathematically intensive, and requires substantial computing power to realize in real-time.Recently, multi-core processors are becoming more prevalent and...
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Hardware Simulator for MIMO Propagation Channels: Time Domain Versus Frequency Domain Architectures
Bachir Habib,
Gheorghe Zaharia,
Ghais El Zein
Issue:
Volume 2, Issue 2, April 2013
Pages:
37-55
Received:
23 April 2013
Accepted:
Published:
2 April 2013
Abstract: A hardware simulator facilitates the test and validation cycles by replicating channel artifacts in a controllable and repeatable laboratory environment. This paper presents an overview of the digital block architectures of Multiple-Input Multiple-Output (MIMO) hardware simulators. First, the simple frequency architecture is presented and analyzed. Then, an improved frequency architecture, which works for streaming mode input signals, is considered. After, the time domain architecture is described and analyzed. The architectures of the digital block are presented and designed on a Xilinx Virtex-IV Field Programmable Gate Array (FPGA). Their accuracy, occupation on the FPGA and latencies are analyzed using Wireless Local Area Networks (WLAN) 802.11ac and Long Term Evolution System (LTE) signals. The frequency and the time approaches are compared and discussed, for indoor (using TGn channel models) and outdoor (using 3GPP-LTE channel models) environments. It is shown that the time domain architecture present the best solution for the design of the architecture of the hardware simulator digital block. Finally, a 2×2 MIMO time domain architecture is described and simulated with input signal that respects the bandwidth of the considered standards.
Abstract: A hardware simulator facilitates the test and validation cycles by replicating channel artifacts in a controllable and repeatable laboratory environment. This paper presents an overview of the digital block architectures of Multiple-Input Multiple-Output (MIMO) hardware simulators. First, the simple frequency architecture is presented and analyzed....
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A Performance Comparison of CMOS Voltage-Controlled Ring Oscillators for its Application to Generation and Distribution Clock Networks
Mónico Linares Aranda,
Oscar González Díaz,
Carlos Ramón Báez Álvarez
Issue:
Volume 2, Issue 2, April 2013
Pages:
56-66
Received:
23 April 2013
Accepted:
Published:
20 May 2013
Abstract: In this work, a performance comparison of expanded CMOS voltage-controlled ring oscillators for non-resonant local clock generation and distribution networks is presented. Several differential and single-ended ring oscillators are designed and fabricated using long interconnection lines to achieve wide coverage chip. A test chip containing the several oscillators was fabricated using an Austria Microsystems (AMS) 0.35 μm CMOS technology. Experimental results show that it is possible to generate and distribute high frequency signals (GHz range) on a relativity large area (coverage) and low phase noise using non-resonant ring oscillators. This represents an attractive alternative for the design and implementation of local Clock Generation and Distribution Networks for systems on chip.
Abstract: In this work, a performance comparison of expanded CMOS voltage-controlled ring oscillators for non-resonant local clock generation and distribution networks is presented. Several differential and single-ended ring oscillators are designed and fabricated using long interconnection lines to achieve wide coverage chip. A test chip containing the seve...
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Survey of Low Power Testing of VLSI Circuits
P. Basker,
A. Arulmurugan
Issue:
Volume 2, Issue 2, April 2013
Pages:
67-74
Received:
13 April 2013
Accepted:
Published:
20 May 2013
Abstract: The System-On-Chip (SoC) revolution challenges both design and test engineers, especially in the area of power dissipation. Generally, a circuit or system consumes more power in test mode than in normal mode. This extra power consumption can give rise to severe hazards in circuit reliability or, in some cases, can provoke instant circuit damage. Moreover, it can create problems such as increased product cost, difficulty in performance verification, reduced autonomy of portable systems, and decrease of overall yield. This paper surveys about the available low power testing techniques during testing. It also suggests some advantages and disadvantages associated with every techniques
Abstract: The System-On-Chip (SoC) revolution challenges both design and test engineers, especially in the area of power dissipation. Generally, a circuit or system consumes more power in test mode than in normal mode. This extra power consumption can give rise to severe hazards in circuit reliability or, in some cases, can provoke instant circuit damage. Mo...
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Implementation of Music Equalization Simulink Model on DSK6713
Issue:
Volume 2, Issue 2, April 2013
Pages:
75-77
Received:
29 April 2013
Accepted:
Published:
30 May 2013
Abstract: Audio equalization is a technique which consists of boosting or cutting certain frequency components of a given signal for sound quality enhancement. Equalizer is an electronic device or type of software that increases and decreases the power of sound waves. The paper deals with the analysis of music signals to develop insight on its frequency bands and auditory perception, through a case study of audio equalization. The graphic equalizer is designed through a Simulink model and is implemented in TMS320C6713 DSP board. This project is developed in order to deliver an insight on how audio equalization can be implemented with Matlab / Simulink for educational purposes.
Abstract: Audio equalization is a technique which consists of boosting or cutting certain frequency components of a given signal for sound quality enhancement. Equalizer is an electronic device or type of software that increases and decreases the power of sound waves. The paper deals with the analysis of music signals to develop insight on its frequency band...
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