Volume 5, Issue 2, April 2016, Page: 8-18
Design Flow Allowing the Effective Use of Non-scan and Scan-Based Tests
Rimantas Seinauskas, Software Department, Informatic Faculty, Kaunas University of Technology, Kaunas, Lithuania
Received: Aug. 15, 2016;       Accepted: Aug. 23, 2016;       Published: Sep. 9, 2016
DOI: 10.11648/j.cssp.20160502.11      View  3347      Downloads  101
At speed delay testing is important for embedded systems. Attempts to solve the problems of delay testing only with non-scan or scan-based tests are unsuccessful. There is no need to oppose these tests, but it is necessary to use both taking full advantage of their opportunities. Design flow and the ability to use non-scan and scan-based ATPG, functional test and fault simulation is presented. The goal is to detect as many faults with non-scan at-speed test. The remaining faults are detected with a scan-based test. As a result, there are less of undetected faults and the length of the scan-based test is reduced. The proposed approach provides more flexibility for test generation. Design flow forced the development of new methods for speeding up fault simulation and for more efficient generation of input patterns. Experimental results demonstrate the possibilities of approach.
Non-scan Test, Scan-Based Test, Functional Test, Design Flow
To cite this article
Rimantas Seinauskas, Design Flow Allowing the Effective Use of Non-scan and Scan-Based Tests, Science Journal of Circuits, Systems and Signal Processing. Vol. 5, No. 2, 2016, pp. 8-18. doi: 10.11648/j.cssp.20160502.11
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This article is an open access article distributed under the Creative Commons Attribution License (http://creativecommons.org/licenses/by/4.0/) which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
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